1. Field of the Invention
The present invention relates to a multimedia digital broadcasting receiver and, more particularly, to a lock detecting apparatus and method for a multimedia digital broadcasting receiver.
2. Description of the Related Art
A quadrature amplitude modulation (QAM) receiver is designated as the standard transmission system for cable channels in a digital television. Generally, the QAM receiver has a carrier recovery unit and a channel equalizer which primarily are used to remove noises such as frequency offset, phase offset, and ghost to minimize a mean-squared error (MSE). Accordingly, a criterion for determining whether the carrier recovery unit and the channel equalizer have removed such errors is required. Namely, a lock detector is required.
To enhance a bit error rate (BER) of the system after a pull-in of a corresponding noise, the carrier recovery unit uses gear shifting. The gear shifting method shifts a phase error detection algorithm from a blind mode to a decision-directed mode, thereby gradually decreasing the noise bandwidth of a loop filter. Such mode conversion method may be divided into a manual and automatic methods.
Compared to the automatic mode conversion method, the manual method is not as effective in coping with the randomness of a channel environment and system. Thus, the manual mode conversion method is usually inapplicable in communication modulation such as VSB, QAM, and QPSK. For this reason, most systems implement the automatic mode conversion method, which is realized by a lock detector.
FIG. 1 is a diagram of the lock detector of a multimedia digital broadcasting receiver in the related art comprising an analog/digital (A/D) converter 1, a first mixer 2, a first filter 3, a second mixer 4, a second filter 5, a channel equalizer 6, a first lock detecting unit 7, a phase/frequency error detecting unit 8, a decision device 9, a second lock detecting unit 10, a loop filter 11, and a numerical control oscillator 12. FIG. 2 is a diagram of the second lock detector unit 10 shown in FIG. 1, comprising first to third comparators 10axcx9c10c, fourth to sixth comparators 10dxcx9c10f, first to fourth arithmetic units 10gxcx9c10i, a logic operator 10k, and a reliability counter 101. FIG. 3 is a diagram of a situation when constellations are rotating with a frequency offset of 256QAM.
The operation of the lock detector of a multimedia digital broadcasting receiver in the related art will next be explained with reference to FIGS. 1xcx9c3.
First, the A/D converter 1 converts receives and converts a QAM signal to a corresponding digital signal. The first mixer 2 mixes an intermediate frequency (IF) QAM signal converted by the A/D converter 1 with COS(xcfx86) and outputs a first mixed signal. The first filter 3 removes noises from the first mixed signals output by the first mixer 2 and band filters the noise-removed first mixed signals to output a first filtered signal. The second mixer 4 mixes the IF QAM signal from the A/D converter 1 with SIN(xcfx86) and outputs a second mixed signal. The second filter 5 removes noise from the second mixed signal and band filters the noise-removed second mixed signals to output a second filtered signal. Here, the first and second filters 3 and 5 are square root RC filters.
Thereafter, the channel equalizer 6 changes from a blind mode to a decision-direct mode and converts the filter structure in order to enhance the BER performance of the system after removing noises, i.e. ghost, included in the signals filtered by the first and second filters 3 and 5. To automatically control the conversion from the blind mode to the decision-direct mode, the first lock detecting unit 7 detects the signal from the channel equalizer 6.
The phase/frequency error detector 8 detects phase/frequency errors from the signal output by the channel equalizer 6 to generate a demodulated signal constellation. The decision device 9 detects and outputs a decision constellation based on the demodulated signal constellation from the phase/frequency error detector 8. Finally, the second lock detecting unit 10 detects variations in the demodulated signal constellation from the phase/frequency error detector 8 and in the decision constellation from the decision device 9.
Particularly, as shown in FIG. 2, the first to third comparators 10axcx9c10c in the second lock detecting unit 10 compare the position of the rotating demodulated constellation signal (I_Constellation) output by the phase/frequency error detector 8 with a positive axis of the in-phase axis, 0 and a negative axis corresponding to the positive axis. The fourth to sixth comparators 10dxcx9c10f compare the position of the rotating demodulated constellation signal (Q_Constellation) output by the phase/frequency error detector 8 with a positive axis of the quadrature-phase axis, 0 and a negative axis. The orbit of an energy band of the rotating constellation will be detected according to Equation 1 below.
E={square root over ((I_constellation2+Q_constellation2)}xe2x80x83xe2x80x83[Equation 1]
Thereafter, the first arithmetic unit 10g performs an operation on signals output by the first and fifth comparators 10a and 10e. Namely, the first arithmetic unit 10g uses a multiplier to multiply the output signal of the first comparator 10a by the output signal of the fifth comparator 10e, and generates a resulting signal Window_1. Similarly, the second arithmetic unit 10h uses a multiplier to multiply the output signal of the second comparator 10b by the output signal of the fourth comparator 10d, and generates a resulting signal Window_2. The third arithmetic unit 10i uses a multiplier to multiply the output signal of the third comparator 10c by the output signal of the fifth comparator 10e, and generates the resulting signal Window_3. The fourth arithmetic unit 10j uses a multiplier to multiply the output signal of the second comparator 10b by the output signal of the sixth comparator 10f, and generates the resulting signal Window_4.
Also, the first to sixth comparators 10axcx9c10f and the first to fourth arithmetic units 10gxcx9c10j are configured to program a quantitative value of a window size to be within 4QAM and 256QAM.
The logic operator 10k performs a logic operation to the signals output by the first to fourth arithmetic units 10g xcx9c10j. Namely, the logic operator 10k is an OR gate that performs an OR operation on signals Window_1 to Window_4 output by the first to fourth arithmetic units 10gxcx9c10j to generate, for any one window, a xe2x80x9clogical 1xe2x80x9d upon receiving a rotating demodulated constellation signal or a xe2x80x9clogical 0xe2x80x9d upon failure of receiving a constellation signal.
The reliability counter 101 counts the signals output by the logic operator 10k based on a symbol clock for a predetermined period of time. Particularly, the reliability counter 101 enables a lock detection when a xe2x80x9clogical 0xe2x80x9d occurs for the predetermined time while counting the signals from the logic operator 10k based on the symbol clock. The reliability counter 101 disables a lock detection when a xe2x80x9clogical 1xe2x80x9d occurs for the predetermined time while counting the signals from the logic operator 10k based on the symbol clock.
Generation of the xe2x80x9clogical 1xe2x80x9d from the reliability counter 101 implies that the noises are still in a pull-in state in the carrier recovery block and that it is not time for switching the pull-in noise bandwidth of the loop filter 11. After an elapse of time, upon a pull-in of the noises in the carrier recovery block, the orbit of the energy band would no longer rotate and would become nearly in a form of a square. Thus, the reliability counter 101 would generate xe2x80x9clogical 0xe2x80x9d. As a result, the carrier recovery enables lock detection and gear-shifts the pull-in noise bandwidth of the loop filter 11 to a locking noise bandwidth in order to reduce RMS jitter.
Thereafter, the loop filter 11 filters the loop bandwidth of the signal output by the phase/frequency error detector 8 based on the output signal of the lock detecting unit 10. Here, the loop filter 11 performs gear shifting by filtering the loop bandwidth of the signal output from the phase/frequency error detector 8 based on the signal lock_detection output by the lock detecting unit 10. The numerical control oscillator 12 then generates a desired frequency based on the gear-shifted signal of the loop filter 11. Finally, the A/D converter 1 receives and converts a QAM signal to a corresponding digital signal based on the desired frequency of the numerical control oscillator 12. Subsequently, the process repeats again as described above.
However, a lock detecting apparatus of the multimedia digital broadcasting receiver in the related art as described above has some drawbacks. First, the lock detecting apparatus may be adaptable to a carrier detector but is inapplicable to a channel equalizer. Also, the apparatus uses only a single lock threshold value in the pull-in and the lock-in, which leads to a deterioration of the reliability.
Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the present invention is to provide an effective lock detecting apparatus and method for a multimedia digital broadcasting receiver.
Another object of the present invention is to provide a more reliable lock detecting apparatus and method.
Another object of the present invention is to provide a lock detecting apparatus and method applicable to a channel equalizer as well as a carrier recovery unit.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a lock detecting apparatus for a multimedia digital broadcasting receiver, which has a channel equalizer and a carrier recovery unit, includes a symbol determiner for generating a decision symbol D_I and D_Q based on a baseband digital signal R_I and R_Q output from the carrier recovery unit; and a lock detecting unit for determining lock control signals LD0, LD1 and LD2 based on the baseband digital signal R_I and R_Q output from the carrier recovery unit and based on the decision symbol D_I and D_Q output from the symbol determiner to generate a selected lock control signal for the channel equalizer and the carrier recovery unit.
The lock detecting unit according to the present invention includes a mean squared error (MSE) calculator for calculating a symbol-based MSE based upon the baseband digital signal R_I and R_Q of a derotator and based upon the decision symbol D_I and D_Q output from the symbol determiner; a threshold-calculator for comparing the symbol-based MSE of the MSE calculator with a pre-calculated MSE to determine whether a locking requirement is met, and generating a corresponding control signal; and a reliability count calculator for counting the control signal output from the threshold calculator for a predetermined time to generate a signal corresponding to the lock control signals LD0, LD1 and LD2.
In the present invention, the lock control signals LD0, LD1 and LD2 may be dependent on a blind mode or a decision-direct mode.
Also, the MSE calculator includes a first subtracter for subtracting the baseband digital signal R_I of the derotator from the decision symbol D_I of the symbol determiner; a first squarer for squaring the output signal of the first subtracter; a second subtracter for subtracting the baseband digital signal R_Q of the derotator from the decision symbol D_Q of the symbol determiner; a second squarer for squaring the output signal of the second subtracter; a mixer for mixing the output signals of the first and second squarers; and a sign expansion bit remover for removing a sign expansion bit from the mixed signal of the mixer.
The threshold calculator includes a MSE ROM table for storing the pre-calculated MSE for 4QAM, 16QAM, 64QAM and 256QAM; first and second comparators for comparing the pre-calculated MSE of the MSE calculator with the MSE stored in the MSE ROM table; and a multiplexer (MUX) for selecting one of either the output signals of the first and second comparators based on the control signal output from the reliability count calculator.
Finally, the reliability count calculator includes a reliability counter for counting the control signals output from the threshold calculator for a predetermined time to determine reliability.
Furthermore, the lock detecting unit sequentially performs a pull-in, a first lock-in, a second lock-in, and a locked-in. Moreover, shifting from the pull-in to the first lock-in step is dependent on the lock control signals LD0, LD1 and LD2; and shifting from the first lock-in to the second lock-in, and from the second lock-in to the locked-in are determined by an internal timer and the lock control signals LD0, LD1 and LD2.
Similar to the apparatus as described above, a lock detecting method for a multimedia digital broadcasting receiver according to the present invention comprises removing an ISI from a baseband digital signal at the channel equalizer based on a lock control signal to generate an ISI-removed baseband digital signal; removing a frequency offset from the ISI-removed baseband digital signal at the carrier recovery unit based on said lock control signal to generate baseband digital signals R_I and R_Q; generating a decision symbol D_I and D_Q based on the baseband digital signal R_I and R_Q; and generating the lock control signal based on the baseband digital signal R_I and R_Q and the decision symbol D_I and D_Q.
By using two threshold values, namely a threshold value for the blind mode and a second threshold value for the decision-direct mode to control both the channel equalizer and the carrier recovery unit, the reliability of the lock detecting unit is enhanced.